1. Field of the Invention
The present invention generally relates to a multi-stage network, and more particularly relates to an apparatus of multi-stage network for iterative decoding and method thereof.
2. Description of the Prior Art
FIG. 1 is a conventional communication system. The data in data source 11 transmitted through channel 14, wherein the data are interfered to cause incorrect data. For receiver getting correct data, Forward Error Correction technique is used to process data. The turbo encoder 12 is an example of such technique. The encoded data are modulated in modulator 13, and then they are sent to receiver via channel 14. The receiver receives data and demodulates them on demodulator 15, and then a turbo decoder 16 decodes data to obtain correct data 17. Thus the communication system with turbo decoder can reduce the error probability of data due to channel 14.
The turbo decoder has good capabilities for error correction in above mentioned communication system. The memories, interleavers, and SISO decoders are the main components in a turbo decoder. The received data will be stored in memories initially, and they are sent to the component soft-in soft-out (SISO) decoders to get some estimated value of the received codeword. It is a tendency to achieve high throughput by dividing a codeword into several partitions, letting these partitions be stored in multiple memories, and decoding these partitions simultaneously on multiple soft-in soft-out (SISO) decoders. However, conventional interleavers can not support this parallel architecture because they lead to some collisions while accessing the received data from memories, passing the data to parallel SISO decoders, and writing the decoding results back to memories.
Some contention-free interleavers are proposed to solve the collision problem. It is trivial to use an appropriate network 22 as the data bus to connect the multiple soft-in soft-out (SISO) decoders 21 and multiple memories 23 for each contention-free interleaver. The interconnection depends on the characteristics of different contention-free interleavers. As the number of the parallel components increases, the complexity of the network also increases. Although a fully-connected network can support all possible interconnections for various interleavers, it has some difficulties in implementation, such as hardware loading, control signal generation, and routing complexity. A low-complexity network which supports the required interconnection patterns is preferred.
The present invention provides a simple apparatus of network for iterative decoding, especially for the application of high parallel architectures. Moreover, two embodiments for the parallel architectures are given.